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ML144110 ML144111
Digital-to-Analog Converters with Serial Interface
CMOS LSI
Legacy Device: Motorola/Freescale MC144110, MC144111
The ML144110 and ML144111 are low-cost 6-bit D/A converters with serial interface ports to provide communication with CMOS microprocessors and microcomputers. The ML144110 contains six static D/A converters; the ML144111 contains four converters. Due to a unique feature of these DACs, the user is permitted easy scaling of the analog outputs of a system. Over a 5 to 15 V supply range, these DACs maybe directly interfaced to CMOS MPUs operating at 5 V . * * * * * * * * Direct R-2R Network Outputs Buffered Emitter-Follower Outputs Serial Data Input Digital Data Output Facilitates Cascading Direct Interface to CMOS P Wide Operating Voltage Range: 4.5 to 15 V Wide Operating Temperature Range: TA = 0 to 85C Software Information is Contained in Document M68HC11RM/AD
18 1
MC144110
P DIP 18 = VP PLASTIC DIP CASE 707
20 1
SO 20W = -6P SOG PACKAGE CASE 751D
MC144111 P DIP 14 = CP PLASTIC DIP CASE 646
14
BLOCK DIAGRAM
VDD Q1 OUT Qn Rn R1 OUT OUT OUT
1
16 1
SO 16W = -5P SOG PACKAGE CASE 751G
2R R 2R 2R R 2R R 2R R 2R R 2R
CROSS REFERENCE/ORDERING INFORMATION PACKAGE MOTOROLA LANSDALE P DIP 18 MC144110P ML144110VP SO 20W MC144110DW ML144110-6P P DIP 14 MC144111P ML144111CP SO 16W MC144111DW ML144111-5P
HEX BUFFER (INVERTING)
Note: Lansdale lead free (Pb) product, as it becomes available, will be identified by a part number prefix change from ML to MLE.
ENB
C
HEX LATCH
CLK
C
*
C D 6-BIT SHIFT REGISTER Dout
DQ Din * Transparent Latch
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PIN ASSIGNMENTS ML144110VP
Din Q1 Out R1 Out Q2 Out R2 Out Q3 Out R3 Out ENB VSS 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 VDD Dout R6 Out Q6 Out R5 Out Q5 Out R4 Out Q4 Out CLK Din Q1 Out R1 Out Q2 Out R2 Out Q3 Out R3 Out ENB VSS NC
ML144110-6P
1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDD Dout R6 Out Q6 Out R5 Out Q5 Out R4 Out Q4 Out CLK NC
ML144111CP
Din Q1 Out R1 Out Q2 Out R2 Out ENB VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD Dout R4 Out Q4 Out R3 Out Q3 Out CLK Din Q1 Out R1 Out Q2 Out R2 Out ENB VSS NC
ML144111-5P
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD Dout R4 Out Q4 Out R3 Out Q3 Out CLK NC
NC = NO CONNECTION
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MAXIMUM RATINGS* (Voltages referenced to VSS)
Parameter DC Supply Voltage Input Voltage, All Inputs DC Input Current, per Pin Power Dissipation (Per Output) TA = 70C, MC144110 MC144111 TA = 85C, MC144110 MC144111 Power Dissipation (Per Package) TA = 70C, MC144110 MC144111 TA = 85C, MC144110 MC144111 Storage Temperature Range Symbol VDD Vin I POH 30 50 10 20 PD 100 150 25 50 Tstg - 65 to + 150 C mW Value - 0.5 to + 18 - 0.5 to VDD + 0.5 10 Unit V V mA mW This device contains protection circuitry to guard against damage due to high static voltages or electric fields; however, it is advised that precautions be taken to avoid application of voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation it is recommended that Vin and Vout be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD).
* Maximum Ratings are those values beyond which damage to the device may occur.
ELECTRICAL CHARACTERISTICS (Voltages referenced to VSS, TA = 0 to 85C unless otherwise indicated)
Symbol VIH Parameter High-Level Input Voltage (Din, ENB, CLK) Test Conditions VDD 5 10 15 5 10 15 Vout = VDD - 0.5 V Vout = 0.5 V Iout = 0 A Vin = VDD or 0 V See Figure 1 5 5 15 15 15 5 10 15 5 10 15 -- 15 -- -- Min 3.0 3.5 4 -- -- -- - 200 200 -- -- -- -- -- -- 19 39 58 -- -- 40 0.4 Max -- -- -- 0.8 0.8 0.8 -- -- 12 8 1 100 200 300 137 274 411 1 10 -- 0.7 Unit V
VIL
Low-Level Input Voltage (Din, ENB, CLK)
V
IOH IOL IDD Iin Vnonl
High-Level Output Current (Dout) Low-Level Output Current (Dout) Quiescent Supply Current ML144110 ML144111
A A mA A mV
Input Leakage Current (Din, ENB, CLK) Nonlinearity Voltage (Rn Out)
Vstep
Step Size (Rn Out)
See Figure 2
mV
Voffset IE hFE VBE
Offset Voltage from VSS Emitter Leakage Current DC Current Gain Base-to-Emitter Voltage Drop
Din = $00, See Figure 1 VRn Out = 0 V IE = 0.1 to 10.0 mA TA = 25C IE = 1.0 mA
LSB A -- V
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SWITCHING CHARACTERISTICS
(Voltages referenced to VSS, TA = 0 to 85C, CL = 50 pF, Input tr = tf = 20 ns unless otherwise indicated) Symbol twH Parameter Positive Pule Width, CLK (Figures 3 and 4) VDD 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 - 15 5 - 15 Min 2 1.5 1 5 3.5 2 5 3.5 2 1000 750 500 5 3.5 2 5 3.5 2 -- -- Max -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 2 7.5 Unit s
twL
Negative Pulse Width, CLK (Figure 3 and 4)
s
tsu
Setup Time, ENB to CLK (Figures 3 and 4)
s
tsu
Setup Time, Din to CLK (Figures 3 and 4)
ns
th
Hold Time, CLK to ENB (Figures 3 and 4)
s
th
Hold Time, CLK to Din (Figures 3 and 4)
s
tr, tf Cin
Input Rise and Fall Times Input Capacitance
s pF
OUTPUT VOLTAGE @ Rn Out, % (VDD - VSS )
100
75
Vnonl ACTUAL
50
IDEAL
25 Voffset 0
0 $00
15 $0F
31 $1F PROGRAM STEP
47 $2F
63 $3F
LINEARITY ERROR (integral linearity). A measure of how straight a device's transfer function is, it indicates the worst-case deviation of linearity of the actual transfer function from the best- fit straight line. It is normally specified in parts of an LSB.
Figure 1. D/A Transfer Function
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VRn OUT
STEP SIZE Step Size =
VDD 0.75 VDD 64 64
(For any adjacent pair of digital numbers) DIGITAL NUMBER
Figure 2. Definition of Step Size
ENB
50%
tsu CLK 50% C1 twH twL C2 CN
th
Din tsu
D1 th
D2
DN
Figure 3. Serial Input, Positive Clock
ENB
tsu CLK C1 twL twH C2 CN
th
Din
D1 tsu
D2 th
DN
Figure 4. Serial Input, Negative Clock
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PIN DESCRIPTIONS INPUTS Din Data Input Six-bit words are entered serially, MSB first, into digital data input, Din. Six words are loaded into the ML144110 during each D/A cycle; four words are loaded into the ML144111. The last 6-bit word shifted in determines the output level of pins Q1 Out and R1 Out. The next-to-last 6-bit word affects pins Q2 Out and R2 Out, etc. ENB Negative Logic Enable The ENB pin must be low (active) during the serial load. On the low-to-high transition of ENB, data contained in the shift register is loaded into the latch. CLK Shift Register Clock Data is shifted into the register on the high-to-low transition of CLK. CLK is fed into the D-input of a transparent latch, which is used for inhibiting the clocking of the shift register when ENB is high. The number of clock cycles required for the ML144110 is usually 36. The ML144111 usually uses 24 cycles. SeeTable 1 for additional information.
OUTPUTS Dout Data Output The digital data output is primarily used for cascading the DACs and may be fed into Din of the next stage. R1 Out through Rn Out Resistor Network Outputs These are the R-2R resistor network outputs. These outputs may be fed to high-impedance input FET op amps to bypass the on-chip bipolar transistors. The R value of the resistor network ranges from 7 to 15 k. Q1 Out through Qn Out NPN Transistor Outputs Buffered DAC outputs utilize an emitter-follower configuration for current-gain, thereby allowing interface to low-impedance circuits. SUPPLY PINS VSS Negative Supply Voltage This pin is usually ground. VDD Positive Supply Voltage The voltage applied to this pin is used to scale the analog output swing from 4.5 to 15 V p-p.
Table 1. Number of Channels vs Clocks Required
Number of Channels Required 1 2 3 4 5 6 Number of Clock Cycles 6 12 18 24 30 36 Q1/R1 Q1/R1, Q2/R2 Q1/R1, Q2/R2, Q3/R3 Q1/R1, Q2/R2, Q3/R3, Q4/R4 Q1/R1, Q2/R2, Q3/R3, Q4/R4, Q5/R5 Q1/R1, Q2/R2, Q3/R3, Q4/R4, Q5/R5, Q6/R6
Outputs Used on ML144110
Outputs Used on ML144111 Q1/R1 Q1/R1, Q2/R2 Q1/R1, Q2/R2, Q3/R3 Q1/R1, Q2/R2, Q3/R3, Q4/R4 Not Applicable Not Applicable
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OUTLINE DIMENSIONS
P DIP 18 = VP (ML144110VP) PLASTIC DIP CASE 707-02
NOTES: 1. POSITIONAL TOLERANCE OF LEADS (D), SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. MILLIMETERS MIN MAX 22.22 23.24 6.10 6.60 3.56 4.57 0.36 0.56 1.27 1.78 2.54 BSC 1.02 1.52 0.20 0.30 2.92 3.43 7.62 BSC 15 0 0.51 1.02 INCHES MIN MAX 0.875 0.915 0.240 0.260 0.140 0.180 0.014 0.022 0.050 0.070 0.100 BSC 0.040 0.060 0.008 0.012 0.115 0.135 0.300 BSC 0 15 0.020 0.040
18 1
10
B
9
A C L
N F H G D
SEATING PLANE
K M J
DIM A B C D F G H J K L M N
-A-
20 11
SO 20W = -6P (ML144110-6P) SOG PACKAGE CASE 751D-04
-B-
1 10
10X
P 0.010 (0.25)
M
B
M
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.150 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 12.65 12.95 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0 7 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.499 0.510 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0 7 0.395 0.415 0.010 0.029
20X
D
M
0.010 (0.25)
TA
S
B
J
S
F R C -T-
18X SEATING PLANE X 45
G
K
M
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OUTLINE DIMENSIONS
P DIP 14 = CP (ML144111CP) PLASTIC DIP CASE 646-06
14 8
B
1 7
NOTES: 1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE POSITION AT SEATING PLANE AT MAXIMUM MATERIAL CONDITION. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 4. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M N INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.300 BSC 0 10 0.015 0.039 MILLIMETERS MIN MAX 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.62 BSC 0 10 0.39 1.01
A F C N H G D
SEATING PLANE
L
J K M
-A-
16 9
SO 16W = -5P (ML144111-5P) SOG PACKAGE CASE 751G-02
-B-
1 8
8X
P 0.010 (0.25)
M
B
M
16X
D
M
J TA
S
0.010 (0.25)
B
S
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 10.15 10.45 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0 7 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.400 0.411 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0 7 0.395 0.415 0.010 0.029
F R X 45 C -T-
14X
G
K
SEATING PLANE
M
Lansdale Semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Lansdale does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. "Typical" parameters which may be provided in Lansdale data sheets and/or specifications can vary in different applications, and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by the customer's technical experts. Lansdale Semiconductor is a registered trademark of Lansdale Semiconductor, Inc.
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